Distributed DC voltage generator for system on chip

ABSTRACT

A system on a chip (SOC voltage generator) system is provided for supplying at least one voltage level to a plurality of units on a chip having an SOC design. The system includes a plurality of local DC voltage generators distributed throughout the chip, each local DC voltage generator independently supplying voltage to at least one unit of the plurality of units, each local DC voltage generator including a regulator system outputting one pump control signal; and a pump system receiving the one pump control signal and outputting at least one voltage level in accordance with the one pump control signal. Furthermore a method for supplying voltage to a plurality of units on a chip having an SOC design is provided. The method includes the steps of distributing a plurality of local DC voltage generators throughout the chip; and supplying at least one voltage level to the plurality of units via the plurality of local DC voltage generators.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is a Continuation of U.S. patent applicationSer. No. 10/118,753 filed Apr. 9, 2002.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to integrated circuit design, andmore specifically, to a DC voltage generator for a system on chip (SOC).

[0004] 2. Discussion of the Related Art

[0005] When designing and producing digital products, it is an ongoinggoal to minimize size, increase capabilities and minimize powerconsumption. For example, the market calls for smaller and more powerfulhandheld digital products such as cellular phones, pagers, globalpositioning systems (GPS's), personal digital assistants (PDAs), laptopcomputers and palm computers, while minimizing power consumption forextending battery life. To help accomplish this, System on Chip (SOC)design is implemented in which various components, such as volatilememory systems, non-volatile memory systems, data signal processingsystems, mixed signal circuits and logic circuits are each formed intounits and integrated on a single chip. Digital systems using SOC design,such as those used in handheld digital products, has replaced bulkierand higher power consuming digital systems built on a board in a packagehaving several chips. As technology advances, integration of variousunits included in a SOC design becomes increasingly complicated.

[0006] The purpose of a DC voltage generator system on a semiconductorchip is to provide power regulation and power conversion, such as forconverting a voltage provided by an external power supply, to a propervoltage level for performing an operation being executed by the chip.One particular challenge of integrating the various units is theprovision of proper voltage levels to the individual units by an on-chipDC voltage generator system, as the units on the chip have a broad rangeof functionality as well as voltage and power requirements. For example,an embedded DRAM (eDRAM) unit generally requires a high operatingvoltage relative to digital logic circuit units, while analog circuitsof mixed signal units generally require an even higher operatingvoltage. Regarding power requirements, memory units generally requireless power than digital logic circuit units, while analog circuits ofmixed signal units typically require more power than the other units.

[0007] A typical DC voltage generator system includes a central DCvoltage generator having a plurality of regulator systems, and a pumpsystem (also referred to as charge pump) associated with each regulatorsystem. The DC voltage generator system further includes wiring forproviding the voltages provided by the central DC voltage generator tothe units of the chip. The DC voltage generator system having a centralDC voltage generator is cumbersome, and is susceptible to contributingto power supply noise and noise cross-contamination between neighboringunits.

[0008]FIG. 1 shows an exemplary conventional regulator system 30 of anon-chip DC voltage generator system, which is described in U.S. Pat. No.6,060,873, to Temullo, Jr. et al., which is incorporated herein byreference. The regulator system 30 receives a boosted supply voltageV_(H), a supply voltage V_(DD), and a power-up control signal PU, andoutputs a boost control signal BC, which is propagated to a charge pump(not shown). The regulator system 30 is used to convert the externallysupplied power to the voltage and current needed for the chip, whileregulating the voltage with stability and noise reduction. The regulatorsystem 30 controls the charge pump for increasing or decreasing thevoltage output by the charge pump accordingly. The voltage output by thecharge pump is provided to the various units of the chip.

[0009] A further disadvantage of the DC voltage generator system havinga central DC voltage generator is that in order to provide enoughcurrent for full speed operation of the chip, in which one or more unitsoperate in a high performance mode, the DC voltage generator system isusually designed to meet a highest power consumption condition. Thecharge pumps of the central DC voltage generator are controlled to allprovide the same current to the units on the chip, even when one or moreof the units on the chip are operating in a low-performance mode, thuswasting power.

[0010] Furthermore, the conventional DC voltage generator system havinga central DC voltage generator does not generally contribute to powerconservation. For example, in SOC design power conservation isimplemented by using low power systems on chip (LP-SOC), which typicallyuses a low-power architecture. When operating in high performance mode,all units on an LP-SOC chip work at full speed. When switching activityis decreased, in which data processing speed and data input/output slowsdown and some units are disabled, the chip clock slows down in order tosave power. However, the central DC voltage generator operates as usualby providing power to the units, regardless of whether the units aredisabled or the chip clock output is changed, and power may be consumedwithout actually executing data.

[0011] Accordingly, a need exists for a system and a method for an SOCDC voltage generator system having a network of small sized distributedlocal voltage generators providing scalable voltage and power levels todifferent units on the chip. A need further exists for a system andmethod for an SOC DC voltage generator system that is controlled tooperate in accordance with variable performance. Finally, a need existsfor clock gated local voltage generators for individually controllingeach local voltage generator in accordance with a clock signalindicative of a low performance mode.

SUMMARY

[0012] It is an aspect of the present invention to provide a system anda method for an SOC DC voltage generator system having a network ofdistributed local voltage generators providing scalable voltage levelsto different units on the chip.

[0013] It is a further aspect of the present invention to provide asystem and method for an SOC DC voltage generator system that iscontrolled for operating in variable performance modes.

[0014] Finally, it is an aspect of the present invention to provide asystem and method for clock gated local voltage generators forindividually controlling each local voltage generator in accordance witha clock signal indicative of a low performance mode.

[0015] Accordingly, the present invention provides an SOC voltagegenerator system for supplying at least one voltage level to a pluralityof units on a chip having an SOC design. The voltage generator systemincludes a plurality of local DC voltage generators distributedthroughout the chip, each local DC voltage generator independentlysupplying voltage to at least one unit of the plurality of unites, eachlocal DC voltage generator including a regulator system outputting onepump control signal; and a pump system receiving the one pump controlsignal and outputting at least one voltage level in accordance with theone pump control signal.

[0016] Furthermore, the present invention provides a method forsupplying voltage to a plurality of units on a chip having an SOCdesign, the method including the steps of distributing a plurality oflocal DC voltage generators throughout the chip; and supplying at leastone voltage level to the plurality of units via the plurality of localDC voltage generators.

BRIEF DESCRIPTION OF THE FIGURES

[0017] The above and other features of the present invention will becomemore apparent from the following detailed description of preferredembodiments, taken in conjunction with the accompanying drawings, inwhich:

[0018]FIG. 1 is a block diagram of a prior art DC voltage generatorsystem;

[0019]FIG. 2 a block diagram of a chip having a system on chip design inaccordance with the present invention;

[0020]FIG. 3 is a block diagram of a SOC DC voltage generator system inaccordance with the present invention; and

[0021]FIG. 4 is a circuit diagram of a local DC voltage generator inaccordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0022] The present invention provides a distributed DC voltage generatorsystem having a plurality of distributed local DC voltage generators.Each of the local DC voltage generators converts a voltage provided froman external power supply to an appropriate voltage level for anassociated unit of a chip having a system on chip (SOC) design.Furthermore, each local DC voltage is individually controlled inaccordance with a power control signal and a clock control signal.Hence, the distributed DC voltage generator system of the presentinvention provides for provision of a scalable voltage and power levelto individual units of the chip, and individual switching on/off ofvoltage/power provision to individual units for conservation of power.The present invention also provides a preferred method for distributinga scalable voltage and power level to individual units of the chipcontrolled by operating conditions of the chip to reduce powerconsumption, while decreasing power supply noise and noisecross-contamination between neighboring units.

[0023] With reference to FIG. 2, an exemplary chip 200 having an SOCdesign (alternatively referred to as SOC chip or SOC) is shown. The SOCchip 200 includes a variety of units including a mixed signal unit 202,logic circuit units 204, a flash memory unit 206, SRAM units 208, a datasignal processor (DSP) unit 210 and a power control unit (PCU) 220. Eachof the units, other than the power control unit, which receives powerfrom the chip supply voltage, is individually provided with power and/orvoltage from an associated local DC voltage generator 230. There is nopower connection between the units of the SOC chip 200.

[0024] Each of the local DC voltage generators 230 is controlled throughthe PCU 220. The PCU 220 generates power control signals (PCS(x), wherex=1−n for n units) for controlling the local DC voltage generator 230 inaccordance with power saving mode instructions received from an externalsource, in accordance with a determination of performance mode made by asource within the SOC chip 200, or in accordance with a determinationmade by the PCU 220 or a combination thereof. The determination of aperformance mode is in accordance with detected power need, such asdetection of a chip activity level including switching level,input/output (I/O) level and processing level. The PCU 220 determineswhether the SOC chip 200 is operating in a high performance mode or in alow performance mode and decides which of the local DC voltagegenerators can be disabled. For example, if the PCU 220 determines thatthe SOC chip 200 is operating in the low performance mode, the PCU 220generates a “low” PCS(x) to selected units or all of the units. If thePCU 220 determines that the SOC chip 200 is operating the highperformance mode, the PCU 220 generates a “high” PCS(x) to all or someof the units. Thus, the amount of power provided to the units of the SOCchip 200 varies in accordance with the performance level of the SOC chip200.

[0025] In another embodiment, the PCU 220 is capable of recognizing N(where N>=2) performance modes in which the SOC chip 200 is capable ofoperating, and generates the PCS(x) to each local DC voltage generator230 in accordance with the recognized performance mode. The combinationof PCS(1−n) generated to all of the DC voltage generators varies inaccordance with the performance mode recognized by the PCU 220. Thus,the amount of power provided to the units of the SOC chip 200 varies inup to N levels in accordance with the performance level of the SOC chip.

[0026] With reference to FIG. 3, a distributed DC voltage generatorsystem 300 for providing voltage and/or power to the units of the SOCchip 200 is shown. The distributed DC voltage generator system 300includes a plurality of local DC voltage generators 230, the PCU 220 anda clock control unit (CLKCU) 310. The CLKCU 310 maybe an external clockcontrol unit or a clock control macro located on the SOC chip 200, whichreceives and processes an external clock signal, or generates andprocesses a clock signal. The CLKCU 310 generates a combined clockenable signal (CES) which is divided into individual signals CES(x),where x=1−n, corresponding to n DC voltage generators 230. Furthermore,each CES(x) signal is preferably provided to the unit associated withthe DC voltage generator 230 receiving the CES(x) signal. The PCU 220and the CLKCU 310 generate individual signals PCS(x) and CES(x) to eachof the local DC voltage generators 230 for independently controlling theDC voltage generators 230. Each CES(x) and PCS(x) controls the on/offswitch of the DC voltage generators 230 receiving the signal.

[0027] It is contemplated that control signals PCS(x) and CES(x), aloneor in combination, may control different modes of operation of the localDC voltage generator 230 receiving the control signals CES(x) and/orPCS(x).

[0028] In order to provide the proper voltage level(s) to each unit,each local DC voltage generator 230 preferably includes a voltage pumpsystem 320 for generating one or more operating voltages. The voltagepump system provides the ability to provide a higher operating voltagelevel to a unit such as the mixed signal unit 202, and differentoperating voltage levels (e.g., Vbb, Vneg and Vpp) for within a unitsuch as a unit having an embedded DRAM macro.

[0029] It is contemplated that a local DC voltage generator 230 mayprovide voltage and/or power voltage level to one or more units. Thelocal DC voltage generator may include a pump system for providing oneor more voltage levels.

[0030]FIG. 4 shows an exemplary local DC voltage generator 230 includingAND gate GI, FET devices F1-3, Capacitor C1 and regulator system 412.PCS(x) and CES(x) are received by G1 which outputs control signal CS(x)for controlling FET F3, preferably an nFET, which switches the regulatorsystem 412 on or off. When either of PCS(x) and CES(x) are “low”, CS(x)switches FET F3 “off” so that no DC current flows to the regulatorsystem 412. When both PCS(x) and CES(x) are “high”, CS(x) switches FETF3 “on” and power supply voltage V_(H) is provided to the regulatorsystem 412. FET devices F1, F2, which are preferably pFET devices, arecascade transistors functioning as a voltage divider, where the amountof voltage passing through the FET devices F1, F2 is determined by thesize of the FET devices F1, F2 (in a way similar to relatively bulkyresistors). Preferably, the FET devices F1 and F2 are different sizes.Capacitor C1 is a decoupling capacitor for reducing power supply noisedue to wiring inductance along a supply line connecting the power supplyto the regulator system 412. Wiring inductance is further minimized bymaintaining the supply line to be short.

[0031] The regulator system 412 may be a conventional regulator systemsuch as the prior art regulator system 30 shown in FIG. 1. The regulatorsystem 412 of the local DC voltage generator 230 associated with eachunit may be customized to provide the proper voltage level required bythat unit. A voltage V₁ indicative of the power supply voltage V_(H) isprovided to a voltage divider (not shown, similar to VD 11 of FIG. 1) ofthe regulator system, and is compared to a reference voltage fordetermining the value of the output control signal BC which controls acharge pump (not shown) for outputting the proper voltage level to theunit. The voltage level output to the unit is selectable by selectingthe reference voltage. Thus, the voltage level output by each local DCvoltage generator 230 is selectable by selecting the reference voltagefor the regulator system 412 of the local DC voltage generator 230. Asmentioned above, the charge pump may be a charge pump system capable ofproviding different operating voltage levels to one unit, such as Vbb,Vneg and Vpp.

[0032] When either the PCS(x) and CES(x) signal are “low” and CS(x) is“low”, current does not flow to the voltage divider of the regulatorsystem 412 and thus to the regulator system 412, and therefore currentflow in the local Dc voltage generator 230.

[0033] The distributed DC voltage generator system 200 provides furtheradvantages including power supply noise reduction due to locallysupplied power, where the power may be supplied from the nearest supplypins. In addition, noise cross-contamination between neighboring unitsis virtually eliminated as there is no power connection between theunits due to independent connections between the units and the powersource.

[0034] What has been described herein is merely illustrative of theapplication of the principles of the present invention. For example, thesystems described above and implemented as the best mode for operatingthe present invention are for illustration purposes only. For instance,other design configurations may be used which provide similar operationas the system described herein. In other words, other arrangements andmethods may be implemented by those skilled in the art and arecontemplated to be within the scope of the appended claims.

In the claims:
 1. A system on chip (SOC) DC voltage generator system forsupplying at least one voltage level to a plurality of subsystems on achip having an SOC design, each of the subsystems having a plurality ofunits, the DC voltage generator system comprising: a plurality of localDC voltage generators distributed throughout the chip, each local DCvoltage generator independently supplying voltage to at least one unitof the plurality of subsystems, each local DC voltage generatorincluding: at least one regulator system incorporated in a section ofthe local DC voltage generator, a power control unit and a clock controlunit, wherein each regulator system receiving a clock control signalfrom said power control and clock control units and outputting one pumpcontrol signal from the section of the local DC voltage generator, thepump control signal being based on the clock control signal; and a pumpsystem receiving the one pump control signal and outputting at least onevoltage level in accordance with the one pump control signal.
 2. The SOCDC voltage generator system according to claim 1, wherein each local DCvoltage generator is located proximate to a unit of the plurality ofunits.
 3. The SOC DC voltage generator system according to claim 1,wherein each local DC voltage generator supplies the voltage level toone unit of the plurality of units.
 4. The SOC DC voltage generatorsystem according to claim 1, wherein a voltage level of the voltagesupplied is selectable.
 5. The SOC DC voltage generator system accordingto claim 1, wherein each local DC voltage generator is independentlycontrolled by a respective control signal.
 6. The SOC DC voltagegenerator system according to claim 5, wherein each respective controlsignal is generated by a power control unit in accordance with a powerlevel mode at which the chip is operating.
 7. The SOC DC voltagegenerator system according to claim 6, wherein the power control unitreceives instructions from an external source for determining the powerlevel mode.
 8. The SOC DC voltage generator system according to claim 5,wherein each respective control signal is generated by a clock controlunit.
 9. The SOC DC voltage generator system according to claim 5,wherein each respective control signal is generated in accordance withan activity level of the chip.
 10. The SOC DC voltage generator systemaccording to claim 9, wherein the activity level is one of a switchingactivity level and an I/O activity level.
 11. The SOC DC voltagegenerator system according to claim 8, wherein the respective controlsignal controlling one of the local DC voltage generators is provided tothe unit associated with the local DC voltage generator.
 12. The voltagegenerator system according to claim 5, wherein each respective controlsignal controls current flow in the local DC voltage generator.
 13. Amethod for supplying voltage to a plurality of subsystems on a chiphaving an SOC design, each of the subsystems having a plurality ofunits, the method comprising the steps of: distributing a plurality oflocal DC voltage generators throughout the chip; supplying a clockcontrol signal to each of the local DC voltage generators; generating,in a section of each local DC voltage generator, a pump control signal;receiving, with a pump system of each local DC voltage generator, thepump control signal; generating, using the pump system, a DC voltagebased on the pump control signal; and supplying the generated DC voltageto the plurality of units of said plurality of subsystems.
 14. Themethod of claim 13, further comprising the step of independentlycontrolling each local DC voltage generator of the plurality of DCvoltage generators.
 15. The method of claim 13, further comprising thestep of independently selecting a voltage level to be supplied by eachlocal DC voltage generator.
 16. The method of claim 14, wherein the stepof independently controlling includes controlling each local DC voltagegenerator in accordance with a power mode of the chip.
 17. The method ofclaim 17, wherein the step of independently controlling includescontrolling each local DC voltage generator in accordance with a clockcontrol signal.
 18. The method of claim 17, wherein the clock controlsignal is further provided to selected units of the plurality of units.19. The method of claim 14, wherein the step of independentlycontrolling includes controlling each local DC voltage generator inaccordance with an activity level of the chip.
 20. The method of claim19, wherein activity level is one of a switching level and an I/O levelof the chip.
 21. The method of claim 1, wherein the pump control signalis based on the clock control signal to accommodate different systemoperating modes selected from one of high performance mode and low-powermode.